| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 31 | Design and Implementation of FPGA Based 32-Bit Barrel Shifter Authors:K. NIRANJAN REDDY, S. KIRAN BABU |
0169-0171 |
Download | |
| IJVDCS 32 | VLSI Implementation of Knowledge Based Neural Network Back Propagation Authors:B. PRIYANKA, J. SIVA SANKARI |
0172-0175 |
Download | |
| IJVDCS 33 | Bloom Filter with Novel Parallel Prefix Tree Comparator Authors:R. LOGAPRABHAVATHY, R. VINODHA |
0176-0178 |
Download | |
| IJVDCS 34 | Online Modulation Recognition of Analog Communication Signals using Neural Network Authors:SALIVENDRA SUBRAHMANYA SASTRY, A. KRANTHI KUMAR |
0179-0185 |
Download | |
| IJVDCS 35 | Reduction off State Leakages using Power Gating Techniques Authors:THIRUPATAIAH PERLA |
0186-0189 |
Download | |
| IJVDCS 36 | Design of 32-Bit Carry Propagation Adder using CMOS and Transmission Gate Logic Authors:S. SHARMILA DEVI, K. P. PAVITRA, M. MEGHALA, S. PRIYANGA |
0190-0193 |
Download | |
| IJVDCS 37 | Implementation of High Performance 64-Bit MAC Unit using Hybrid Carry Select Adder Authors:SATHEESH. K, P. P. NAGARAJA RAO |
0194-0197 |
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| IJVDCS 38 | VLSI Implementation of Low Power Pulse-Triggered Static Flip-Flops On Single Feed Through Scheme Authors:HIMAYTULLA SHAIK, K.KISHORE KUMAR |
0198-0202 |
Download | |
| IJVDCS 39 | A Fuzzy Logic Method for Modulation Classification in Nonideal Environments Authors:A. KRANTHI KUMAR, SALIVENDRA SUBRAHMANYA SASTRY |
0203-0208 |
Download | |
| IJVDCS 40 | Self-Scaled CORDIC Rotators for Trigonometric Computation in DCT Using Selective Iterations Authors:J. JEFFERSON, P. SAKTHIVEL |
0209-0213 |
Download | |
